1. Field of the Invention
This invention relates to a digital signal processing system adapted for realtime processing of digital signals having a larger number of bits per word and a higher word rate per unit time, such as PCM audio signals. More particularly, it relates to such digital signal processing system conveniently applied to a graphic equalizer or echo room with a digital signal delay feature.
2. Description of the Prior Art
In recent years, audio or picture signals are converted into digital signals which then undergo a variety of digital processing or computing operations such as processing by digital filters, fast Fourrier transformation (FFT) or corelative function computing on the realtime basis. Hence, a variety of digital signal processors, hereafter abbreviated sometimes to DSP, have been proposed for performing such realtime processing operations. These DSP's are usually provided with higher precision arithmetic logic units (ALU's), multipliers or other hardware units and controlled by microprograms. In many cases, such digital signal processing is controlled or managed by a host computer system making use of a microprocessor.
These DSP's are provided with internal memories, that is, a microprogram memory and a coefficient memory. The signal processing operation in the DSP's is usually performed in such a manner that microinstructions stored in the microprogram memory are read out sequentially by addresses designated by sequencers or program counters.
System versatility is increased by using random access memories (RAM's) as the aforementioned microprogram memory and coefficient memory, and the data to be entered into these memories may be transferred through control from said host computer system.
In general, realtime processing of the digital signals converted from analog audio or picture signals necessitates fast arithmetic operations such as addition and multiplication, signal delaying and the like processing operations. It has been customary to use a multistage shift registers as hardware or circuitry for causing a delay in the digital signals. In this case, the delay time is expressed as a product of the number of the shift register stages and the sampling period or interval, that is, the period of shift clock pulses.
However, the digital signal delay circuit designed for realtime processing and making use of these shift registers is not subservient to changing the delay time as desired during realtime processing because of the necessity to change the number of the shift registers. In addition, echo rooms or machines formed by a plurality of signal delay lines or circuits tend to be complicated in hardware structure. Above all, with the delay circuits making use of the shift registers, it is practically impossible to effect a dynamic change of the delay time in the respective delay lines. In addition, using a number of shift registers is not economical.
In the conventional DSP's, rewriting the coefficient data, microinstructions etc. during microprogram execution is a desideratum in order to increase the efficiency in realtime processing. However, this is not practically feasible because of oscillations caused by the data becoming discrete especially in the course of rewriting of the coefficient data.
In addition, when the digital signal data is multiplied in the DSP by a coefficient data supplied from the coefficient memory, insufficient word length of the coefficient data may detract from targeted precision of the product especially as a function of the characteristics of digital filters provided in the DSP. On the other hand, multiplier circuits may be extremely complex when the bit numbers of the multiplier and multiplicand are increased to 20 or larger.